On one hand, a metal oxide semiconductor field effect transistor (MOSFET) built on a silicon-on-insulator (SOI) substrate typically offers advantages over a MOSFET with comparable dimensions that is built on a bulk substrate by providing a higher on-current and lower parasitic capacitance between the body and other MOSFET components. On the other hand, a MOSFET built on an SOI substrate tends to have less consistency in the device operation due to “history effect,” or “floating body effect,” in which the potential of the body, and subsequently, the timing of the turn-on and the on-current of the SOI MOSFET are dependent on the past history of the SOI MOSFET. Furthermore, the level of leakage current also depends on the voltage of the floating body, which poses a challenge in the design of a low power SOI MOSFET.
The body of an SOI MOSFET stores charge which is dependent on the history of the device, hence becoming a “floating” body. As such, SOI MOSFETs exhibit threshold voltages which are difficult to anticipate and control, and which vary in time. The body charge storage effects result in dynamic sub-threshold voltage (sub-Vt) leakage and threshold voltage (Vt) mismatch among geometrically identical adjacent devices.
One exemplary semiconductor device in which the floating body effects in SOI MOSFETs are particularly a concern is static random access memory (SRAM) cells, in which Vt matching is extremely important as operating voltages continue to scale down. The floating body also poses leakage problems for pass gate devices. Another exemplary semiconductor device in which the floating body effects are a concern is stacked SOI MOSFET structures, as used in logic gates, in which the conductive state of SOI MOSFET devices higher up in the stack are strongly influenced by stored body charge, resulting in reduced gate-to-source voltage (Vgs) overdrive available to these devices. Yet other exemplary semiconductor devices in which control of the floating body effects is critical are sense amplifiers for SRAM circuits and current drivers in a current mirror circuit.
Referring to FIG. 1, a vertical cross-sectional view of an exemplary prior art SOI MOSFET comprises a semiconductor substrate 8 containing a handle substrate 10, a buried insulator layer 12, and a top semiconductor layer 30. The top semiconductor layer 30 comprises shallow trench isolation 20, a body 32, a deep source region 38A, a deep drain region 38B, a source extension region 34A, a drain extension region 34B, a source side halo region 36A, a drain side halo region 36B, a source metal semiconductor alloy 88A, and a drain metal semiconductor alloy 88B. The shallow trench isolation 20 comprises a dielectric material such as silicon oxide, and laterally surrounds other components of the exemplary prior art SOI MOSFET in the top semiconductor layer 30. The top semiconductor layer 30 excluding the shallow trench isolation 20 and the source metal semiconductor alloy 88A and the drain metal semiconductor alloy 88B comprises a semiconductor material. The source and drain extension regions (34A, 34B) and the source side halo region 36A and the drain side halo region 36B are disjoined from the source metal semiconductor alloy 88A and the drain metal semiconductor alloy 88B.
A gate dielectric 50 is located directly on a portion of the top semiconductor layer 30. A gate electrode 87 abutting the gate dielectric 50 comprises a gate conductor 52 and a gate metal semiconductor alloy 86. At least one gate spacer 55 abuts sidewalls of the gate electrode 87. The at least one gate spacer 55 may comprise a first gate spacer 54 and a second gate spacer 56. The source extension region 34A and the drain extension region 34B are aligned to the sidewalls of the gate electrode 87 and overlaps the gate electric 50 located underneath the gate electrode 87. The source side halo region 36A and the drain side halo region 36B also contact the gate dielectric 50. The body 32, the source side halo region 34A, and the drain side halo region 34B are doped with a first conductivity type doping, which may be p-type doping or n-type doping. The source side halo region 34A and the drain side halo region 34B have a higher doping concentration than the body 32. The deep source region 38A and the deep drain region 38B are doped with a second conductivity doping, which is the opposite of the first conductivity type doping.
The body 32 of the prior art exemplary SOI MOSFET is not electrically connected to the deep source region 38A. The body 32 is, therefore, electrically floating during operation of the prior art exemplary SOI MOSFET. Device characteristics of the prior art exemplary SOI MOSFET suffers from the floating body effects described above.
Methods of reducing floating body effects by incorporating body contacts tied to the source of a partially depleted SOI MOSFET have been proposed to improve performance of the SOI MOSFET. However, prior art methods of tying the body of a partially depleted SOI MOSFET to the source tend to require additional processing steps such as lithographic patterning of an implant area and ion implantation. In addition, the prior art methods also tend to produce inefficient layout due to an additional component to be formed in the SOI MOSFET as well as increased parasitic capacitance due to the presence of the additional component. Thus, the challenge in forming a body contacted SOI MOSFET is to do so without degrading its positive attributes, such as high immunity to short channel effects, steep sub-Vt slope, and high current drive capability due to volume inversion.
In view of the above, there exists a need for a partially depleted semiconductor-on-insulator (SOI) MOSFET having a body electrically tied to the source, while not suffering from adverse effects of prior art body contacted SOI MOSFETs such as requirement for additional processing steps, increased device layout size, and increased parasitic capacitance, and methods of manufacturing such a partially depleted SOI MOSFET.